One or more aspects of the present invention relate generally to delay lines and more specifically to adjustable delay lines and trim units.
Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAS). An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, or the like, though a computer may also be used to provide the bitstream. The collective states of the individual memory cells then determine the function of the FPGA.
Delay lines and trim units are used in integrated circuit (IC) devices such as FPGAs to synchronize clock signals used to clock various circuits therein. For example, delay lines may be used in a wide variety of digital clock management (DCM) circuits to adjust the skew between input and output clock signals.
Delay lines generally provide larger amounts of signal propagation delay with respect to trim units. Delay lines and trim units delay a signal propagating between an input terminal and an output terminal. Fully-digital delay lines are tap-controlled, which typically comprise a large number of delay elements that are commonly referred to as xe2x80x9ctapsxe2x80x9d. Taps generally increment in progressively larger delay values to allow a selection between a minimum delay value and a maximum delay value. Tap-controlled delay lines typically have one or more control inputs configured to select a particular tap, i.e., delay element, and therefore a particular propagation delay amount. To provide a lower propagation delay granularity, a trim unit containing additional delay elements may be added in series with a delay line. Propagation delay for individual delay elements may be changed by increasing or decreasing the size and type of its internal delay circuitry. For example, others have increased the amount of propagation delay of a delay element by adding resistors or transistor-based resistors to one or more delay elements. However, adding resistors, transistor-based resistors, and supporting circuitry consumes additional die space, and may increase jitter. Transistor-based resistors make it difficult to tune delay lines and trim units for consistent operation.
One factor contributing to jitter is local supply noise. Parasitic inductive, capacitive, and resistive loads along the supply lines feeding the delay elements can cause voltage fluctuations, including ground bounce, which increases local power supply noise. Supply noise is proportional to the instantaneous current (di/dt) drawn from the power supply. Little attention is given to local noise generated by other running elements in the trim unit and their corresponding support circuitry in the vicinity of the delay elements. Delay elements of a trim unit responsive to an input signal inherently increase supply noise. For example, conventional trim units using parallel delay elements generally receive an input signal to all of the parallel delay elements. Even though only one delay element is used at a time, all of the delay elements are responsive to the input signal. However, the supply noise of each delay element, used or not, adds to the overall supply noise.
Accordingly, it would be both desirable and useful to provide a trim unit to facilitate circuit tuning, and provide a reduction in jitter and power consumption.
An aspect of the present invention is a trim unit for delaying a clock signal. The trim unit includes a plurality of delay elements. At least one of the plurality of delay elements is controllable between on and off states. The delay elements are controllable such that only one delay element is in the on state at one time. An output circuit having a plurality of inputs and an output is provided. One each of the plurality of inputs is coupled to a respective one of the plurality of delay elements. The output circuit selectively causes an output of a selected one of the plurality of delay elements to drive the output.
An aspect of the present invention is a trim unit configured to delay a clock signal. The trim unit includes a first delay element and a second delay element. A multiplexing circuit having a plurality of inputs and an output is provided. Each of the plurality of inputs is connected to an output of the first delay element and an output of the second delay element. The multiplexing circuit selectively causes the output of a selected one of the first delay element and the second delay element to drive the output. The first delay element and the second delay element are responsive to a control signal such that only one of the first delay element and the second delay element are active at a time. The first delay element and the second delay element include at least one gated delay circuit responsive to the control signal.
An aspect of the present invention is a method for improving jitter in a trim unit. A clock signal is provided to the trim unit. A first delay element and a second delay element are provided in parallel. The first delay element and second delay element are configured to provide different delayed versions of the clock signal. At least one of the first and second delay elements is switchable between on and off states.
An aspect of the present invention is a method for delaying a digital signal. A plurality of delayed versions of the digital signal arranged in parallel having at least a first delay and a second delay are provided. The plurality of delayed versions of the digital signal are provided by a plurality of delay elements. At least one of the delay elements includes a first delay circuit connected to a second delay circuit in series with the first delay circuit. One of the delayed versions of the digital signal is selected. At least one of the delayed versions of the digital signal is switchable between on and off states.